The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
As merely one example, challenges have arisen when attempting to scale image sensor devices. Image sensors are integrated circuits used to detect and measure radiation, such as light, received by the sensor device. These image sensor arrays are incorporated into digital cameras and other consumer devices. One type of sensor, the backside-illuminated (BSI) image sensor, is typically formed on a thin substrate that allows the radiation to reach the sensor by passing through the substrate as opposed to passing through an interconnect structure formed on the opposite or front side of the substrate. The advantage to backside-illuminated devices is that the interconnect structure (which typically includes opaque conductive traces) does not obstruct the incoming radiation. When clustered in an array, individual BSI sensors may be separated by isolation structures to reduce “dark current” (the flow of current when a sensor is not exposed to radiation) and inter-sensor interference. However, as size of an isolation structure is reduced, the amount of isolation provided decreases. Thus, scaling down image sensors can increase unwanted behavior including dark current and sensor noise. Therefore, although existing fabrication process for forming BSI sensors have been generally adequate, they have not proved entirely satisfactory in all respects.